Static charge is an unbalanced electrical charge at rest. Typically, a static charge is created by insulator surfaces rubbing together or pulling apart. One surface gains electrons, while the other surface loses electrons. This results in an unbalanced electrical condition known as the static charge. When a static charge moves from one surface to another, the static charge becomes an electrostatic discharge (ESD). ESD is a miniature “lightning bolt” of charge that moves between two surfaces that have different potentials.
ESD occurs when the voltage differential between the two surfaces is sufficiently high to break down a dielectric strength of the medium separating the two surfaces. When a static charge moves and becomes an ESD, the static charge becomes a current that may damage or destroy gate oxide, metallization, and junctions of circuitry in an integrated circuit, for example. ESD can occur in many ways, for example, a charged body can touch an integrated circuit, a charged integrated circuit can touch a grounded surface, a charged machine can touch an integrated circuit or an electrostatic field can induce a voltage across a dielectric sufficient to break down the dielectric.
ESD events can produce device damage that goes undetected by factory testing, and later, may be the cause of a latent failure in the device. Devices with latent ESD defects are referred to as “walking wounded” because they have been degraded, but not destroyed, by ESD. This occurs when an ESD pulse is not sufficiently strong enough to destroy a device, but nevertheless causes damage. Often, the device suffers junction degradation through increased current leakage or a decreased reverse breakdown, but the device continues to function and is still within data-sheet limits, for example. A device can be subjected to numerous weak ESD pulses, with each successive pulse further degrading a device until a catastrophic failure occurs. There are few practical ways to screen for walking-wounded devices. To avoid this type of damage, devices should be given continuous ESD protection.
To guard against ESD events, integrated circuitry usually is accompanied by an ESD power clamp. Traditional methods of shunting ESD energy to protect circuitry involve devices such as zener diodes, metal oxide varistors (MOVs), transient voltage suppression (TVS) diodes, and regular complementary metal oxide semiconductor (CMOS) or bipolar clamp diodes. However, many of these devices are subject to “glitches,” which include unwanted transitions of a signal from a first voltage state to another, and then back to the first voltage state.
Glitches may be caused by many factors including radiation effects. As such, many circuits are designed to include a level of “radiation hardness,” i.e., an attribute of a circuit indicating the extent to which the circuit can withstand nuclear or other radiation. Integrated digital circuits used in space, weapons, or aviation applications are typically designed to be more resistant to radiation than circuits used in other applications, because they are more likely to be exposed to radiation, and because their reliability is often more critical, for example. However, such solid-state circuits may still be vulnerable to radiation effects, such as disturbances caused by single, charged particles present within an ambient environment of the circuit, such as alpha particles (e.g., byproducts of the natural decay of elements such as uranium and thorium present in some integrated circuit packaging materials) or energetic protons, neutrons, electrons, heavy ions, and all the natural elements (e.g., these are abundant in intergalactic space, earth orbital space and even at high atmospheric or commercial flight altitudes in a wide range of energies).
When a charged particle passes through a transistor (or any active electronic device), the particle loses energy by ionizing the medium through which the particle passes, leaving behind a track of hole-electron pairs. The electrons of the pairs will migrate toward high voltage state nodes of the struck transistor, resulting in a discharging current on that node. If the discharging current exceeds the current drive of the transistor holding the high voltage state on that node, the node will transition to an undesired low state. Conversely, the holes of the pairs will migrate toward low voltage state nodes of the struck transistor resulting in a charging current on that node. If the charging current exceeds the current drive of the transistor holding the low voltage state on that node, the node will transition to an undesired high state. The number of hole-electron pairs created by the particle is finite, so the node voltage disturbance is temporary.
Particle-induced circuit disturbances are random and are commonly referred to as single-event effects (SEEs). The SEEs can take on many forms. If the particle strike results in a bit flip or other form of corruption of stored data, this is known as a single-event upset (SEU), or a soft error. If the particle causes a transient voltage disturbance on a node of a logic circuit, this is known as a single-event transient (SET).
A circuit node will typically return to a desired voltage state after an SET. Thus, an SET, in and of itself, may not be a problem. What is likely to be a problem is the consequence of having a temporary voltage disturbance on a circuit node. As an example, if the node is in an ESD circuit, the disturbance may cause the ESD power clamp to operate incorrectly, and possible allow an ESD to transfer through the circuitry for which the ESD power clamp was designed to protect. Alternatively, the circuitry may be inadvertently triggered if the ESD circuit turns on at a time when system power is applied causing improper operation of the circuitry.
The susceptibility of ESD power clamps to SEEs can be heightened by reduced feature sizes of integrated circuits and higher clock speeds. As feature sizes continue to decrease, SEEs may become more likely to propagate through logic gates as normal logic pulses, causing upsets within logic circuits.
Existing ESD power clamps do not consider possible SEEs. Thus, it is desirable to improve ESD power clamp immunity against an SEE caused by radiation so that a system with ESD power clamp protection may function reliably in a radiation environment.